1. Field of the Invention
The present invention generally relates to oscillator circuits, and particularly relates to an oscillator circuit which generates a signal having a cycle responsive to the charge/discharge operation of a capacitor.
2. Description of the Related Art
In DRAMs using memory capacitors to store data, there is a need to perform a restore operation (i.e., refresh operation) to retain information stored in the cells. Such restore operation includes reading cell data by successively activating word selecting lines, amplifying the data voltage by use of sense amplifiers, and restoring the amplified data to the cells. Refresh operations are periodically performed at predetermined refresh intervals with respect to the memory array or block that is subjected to a refresh operation. An electric current consumed by a refresh operation may be represented as follows.IREF=qREF·NREF/tREF Here, qREF represents the amount of electric charge that is consumed by a single refresh operation (i.e., a refresh operation for one activation of one word line), NREF representing the number of refresh operations (i.e., the number of refresh operations each corresponding to one activation of one word line) performed in one cycle (i.e., in one refresh cycle), and tREF representing a refresh cycle.
In order to reduce the consumed current IREF, it is desirable to prolong the refresh cycle tREF as much as possible within the time period during which the data of DRAM cells can be retained. Since the refresh cycle tREF exhibits variation from circuit to circuit, however, the refresh cycle tREF should be determined so as to provide a margin that takes into account such a variation for the purpose of reliably ensuring that the refresh cycle tREF always stays shorter than the data retainable period. Accordingly, in order to reduce the consumed current IREF by prolonging the refresh cycle tREF as much as possible, there is a need to suppress the variation of the refresh cycle tREF so as to perform each refresh operation at precise cycles.
qREF·NREF becomes larger when the memory capacity is increased, resulting in an increase of an electric current necessary for refresh operations. There will also be an increase in the amount of change in the consumed current IREF responsive to the variation of the refresh cycle tREF. In such a case, a change in the consumed current IREF responsive to the variation of the refresh cycle tREF cannot be disregarded. There is thus a need to set the refresh cycle tREF accurately in order to suppress an increase in current consumption as much as possible.
In the self-refresh mode of a DRAM, a refresh operation is performed at intervals responsive to a cycle of a signal generated by an oscillator inside the DRAM, rather than being performed in response to a refresh command supplied from an external source. FIG. 1 is a drawing showing an example of the configuration of such oscillator (Patent Document 1 through 4).
The oscillator circuit shown in FIG. 1 includes a comparator 11, a constant current source 12, a capacitor 13, a delay circuit 14, a PMOS transistor 15, an NMOS transistors 16, and a NAND gate 17. In the state in which no electric charge is accumulated in the capacitor 13 (capacitance C), a potential vosc at the charge store node of the capacitor 13 is lower than a reference voltage vref. Accordingly, the output of the comparator 11 having an inverted input thereof coupled to the charge store node of the capacitor 13 and a non-inverted input thereof coupled to the reference voltage vref is HIGH, resulting in an oscillator circuit output pulsex being HIGH. In this state, a startup signal startz is changed to HIGH. In response, the output of the NAND gate 17 is changed to LOW, thereby making the NMOS transistors 16 nonconductive. In response to this, an electric current equal in amount to a current amount Icmp of the constant current source 12 flows into the capacitor 13, thereby accumulating electric charge in the capacitor 13.
As the potential vosc of the charge store node of the capacitor 13 exceeds the reference voltage vref, the output of the comparator 11 changes from HIGH to LOW. Subsequently, the oscillator output pulsex changes from HIGH to LOW after the passage of a delay time introduced by the delay circuit 14. In response to this, the output of the NAND gate 17 becomes HIGH to make the NMOS transistors 16 conductive, so that the capacitor 13 is discharged to return to the original state in which no electric charge is accumulated. In response, the output of the comparator 11 returns to HIGH.
In the operation described above, further, the PMOS transistor 15 becomes conductive when the oscillator output pulsex changes from HIGH to LOW, thereby setting the output of the comparator 11 to HIGH. This makes sure than the oscillator output pulsex becomes a pulse signal that sustains its LOW state for a predetermined period corresponding to the delay time of the delay circuit 14 regardless of the response speed of the comparator 11.
The operation described above is repeated so that the oscillator circuit of FIG. 1 outputs pulses at constant time intervals. The cycle (interval) of this pulse is theoretically C·vref/Icmp.
The cycle generated by an oscillator as described above tend to exhibit variation due to variations in the current source, capacitance, reference voltage, comparator offsets, etc. There is thus a need to adjust the oscillating cycle of the oscillator to a desired cycle by measuring the oscillating cycle of the oscillator by use of a tester at a testing step of a circuit (e.g., DRAM) incorporating such oscillator (see Patent Document 5). Arrangement is made in advance such that an oscillating cycle is adjustable by adjusting the current amount of the current source through cutting or leaving intact fuses, for example. The fuses may then be cut as appropriate to achieve a desired cycle based on the checking of the cycle measured by the tester.
When the oscillator circuit shown in FIG. 1 is implemented as a semiconductor device, a MOS transistor is typically used as the capacitor 13. In this case, the capacitance between the gate node and source/drain nodes of the MOS transistor depends on a threshold voltage Vth of the MOS transistor.
FIG. 2 is a drawing showing the capacitance characteristics of a MOS transistor when the threshold voltage Vth of the MOS transistor exhibits variation. In FIG. 2, the horizontal axis represents a gate-source voltage Vgs, and the vertical axis represents a MOS capacitance Cgg. As shown in FIG. 2, when the voltage applied to the gate node (i.e., the gate-source voltage Vgs) is low, no channel is created so that the capacitance Cgg is relatively a small value. As the voltage Vgs become sufficiently large, a channel is created. In response, the capacitance Cgg becomes a relatively large value, which is responsive to the gate length and gate-film width.
In the oscillator circuit shown in FIG. 1, the voltage across the capacitor 13 has a voltage range from 0 V to more than vref. Namely, when the oscillator circuit is oscillating, the voltage Vgs varies in a range that includes a point at which the capacitance Cgg exhibits a large sudden change as shown in FIG. 2.
With a variation in the threshold voltage Vth of the MOS capacitor, the capacitance change relative to the change of the voltage Vgs as shown by the solid lines in FIG. 2 ends up also having a variation as illustrated by dotted lines. Namely, a capacitance characteristic 21 in which the large capacitance appears at a relatively low voltage Vgs is observed in the case of a relatively low threshold voltage Vth. Further, a capacitance characteristic 22 in which the large capacitance appears at a relatively high voltage Vgs is observed in the case of a relatively high threshold voltage Vth.
As a result, the amount of electric charge required for the potential vosc of the charge store node of the capacitor 13 to reach a certain potential ends up varying, so that the potential vosc of the charge store node of the capacitor 13 exhibits variation as shown in FIG. 3. In the case of the capacitance characteristic 21 shown in FIG. 2, the cycle becomes relatively long, resulting in a voltage waveform 23. In the case of the capacitance characteristic 22 shown in FIG. 2, the cycle becomes relatively short, resulting in a voltage waveform 24.
As previously described, the adjustment of the cycle in response to the tester measurements can suppress, to some degree, a cycle variation caused by variation in the threshold voltage Vth. Since the adjustable range is limited, the smaller the variation, the better the outcome will be. Further, the threshold voltage Vth not only varies depending on processes, but also varies depending on temperature. Thus, the cycle also varies depending on temperature. It would be necessary to provide a plurality of adjustment means and to measure temperature at a plurality of measurement points in order to adjust such a variation in the cycle caused by temperature changes. This adds up the test cost.
[Patent Document 1] Japanese Patent Application Publication No. 08-171795
[Patent Document 2] Japanese Patent Application Publication No. 11-168358
[Patent Document 3] Japanese Patent Application Publication No. 8-279733
[Patent Document 4] Japanese Patent Application Publication No. 10-289573
[Patent Document 5] Japanese Patent Application Publication No. 7-220473
Accordingly, there is a need for an oscillator circuit capable of generating an oscillating signal having a predetermined cycle that is not affected by variation in the capacitance characteristics caused by the variation of the threshold voltage Vth.